====== Zynq Ultrascale+ Latch-Up Mitigation Testing ======
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===== Test Desires =====
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  * General:
    * IO testing + MGTs
    * Functionality Testing Before/After beam
    * DDR PS and PS (HD-IOBs)
      * Drew may have something there for before/after testing
      * CF can do in-beam testing with PMU
    * Brown Out Behavior
      * PS vs PL?
      * still like on the pure FPGAs?
  * PS
    * Dynamic Clocking
    * Low Power Operations
    * Lockstep
    * Communication/Interaction PS <=> PL
    * ?Some specific PS hard-interfaces
    * ?PMU behavior
      * it is TMRed, but the rest of the system and all the data path between it and the PL is not ...)
   * PL
     * ?CMTs with the PS/PL interface
     * Ring Oscillators
       * Gary will poke BYU

===== TODO =====
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  * turn this list into something conclusive and concise plan, not just a wishlist


===== Before/After Tests =====

===== In-Beam Tests =====
